1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of making jogged routing layouts that are compliant with double patterning techniques and resulting semiconductor devices that contain such jogged routing layouts.
2. Description of the Related Art
Photolithography is one of the basic processes used in manufacturing integrated circuit products. At a very high level, photolithography involves: (1) forming a layer of light or radiation-sensitive material, such as photoresist, above a layer of material or a substrate; (2) selectively exposing the radiation-sensitive material to a light generated by a light source (such as a DUV or EUV source) to transfer a pattern defined by a mask or reticle (interchangeable terms as used herein) to the radiation-sensitive material; and (3) developing the exposed layer of radiation-sensitive material to define a patterned mask layer. Various process operations, such as etching or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned mask layer.
Of course, the ultimate goal in integrated circuit fabrication is to faithfully reproduce the original circuit design on the integrated circuit product. Historically, the feature sizes and pitches (spacing between features) employed in integrated circuit products were such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced to the point where existing photolithography tools, e.g., 193 nm wavelength photolithography tools, cannot form a single patterned mask layer with all of the features of the overall target pattern. Accordingly, device designers have resorted to techniques that involve performing multiple exposures to define a single target pattern in a layer of material. One such technique is generally referred to as double patterning. In general, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, less-dense patterns. The simplified, less-dense patterns are then printed separately on a wafer utilizing two separate masks (where one of the masks is utilized to image one of the less-dense patterns, and the other mask is utilized to image the other less-dense pattern). Further, in some cases, the second pattern is printed in between the lines of the first pattern such that the imaged wafer has, for example, a feature pitch which is half that found on either of the two less-dense masks. This technique effectively lowers the complexity of the photolithography process, improving the achievable resolution and enabling the printing of far smaller features than would otherwise be possible using existing photolithography tools.
FIG. 1 depicts one illustrative double patterning process. An initial overall target pattern 10 that is comprised of nine illustrative trench features 12 is depicted in FIG. 1. Each of the features 12 has the same critical dimension 13. The space between the features 12 in the initial overall target pattern 10 is such that the initial overall target pattern 10 cannot be printed using a single mask with available photolithography tools. Thus, in this illustrative example, the initial overall target pattern 10 is decomposed into a first sub-target pattern 10A (comprised of features 1, 3, 5, 7 and 9), and a second sub-target pattern 10B (comprised of the features 2, 4, 6 and 8). The sub-target patterns 10A, 10B are referred to as “sub-target patterns” because each of them contain less than all of the features in the initial overall target pattern 10. The features that are incorporated in the sub-target patterns 10A, 10B are selected and spaced such that the patterns 10A, 10B may be readily formed in a single masking layer using available photolithography tools. Ultimately, when the mask design process is completed, data corresponding to the sub-target patterns 10A, 10B (modified as necessary during the design process) will be provided to a mask manufacturer that will produce tangible masks (not shown) corresponding to the patterns 10A, 10B to be used in a photolithography tool to manufacture integrated circuit products.
FIGS. 2A-2B depict various illustrative circuit layout patterns that may be employed when designing integrated circuit devices. FIG. 2A depicts an illustrative circuit layout pattern 14 comprised of a plurality of rectangular line-type features 18, e.g., trenches, and a crossover or jogged feature 16. The crossover or jogged feature 16 is a composite pattern that is comprised of line-type features 16A, 16B that are connected together by a crossover portion 16J. All of the features depicted in FIG. 2A, including the crossover portion 16J, have the same critical dimension 15. The pattern 14 includes five illustrative routing tracks (A-E). The distance between adjacent routing tracks may be referred to as the “pitch” of features in the pattern 14. The crossover feature 16 depicted in FIG. 2A is sometimes referred to as an “even-jog” type feature because the crossover portion 16J spans an even number of pitch distances, e.g., a fist “pitch” between the tracks B and C and a “second pitch” between tracks C and D in the depicted example. A crossover type feature that spanned 6 such pitch distances (not shown) would also be referred to as an even-jog type feature. In contrast, the features 12 depicted in the pattern 10 in FIG. 1 do not have any such crossover or jogged features.
FIG. 2B depicts an illustrative circuit layout pattern 17 comprised of a plurality of rectangular line-type features 19, e.g., trenches, and a crossover or jogged feature 21. The pattern 15 also includes five illustrative routing tracks (A-E). The crossover feature 21 is a composite pattern that is comprised of line-type features 21A, 21B that are connected together by a crossover portion 21J. All of the features depicted in FIG. 2B, including the crossover portion 21J, have the same critical dimension 21X. The crossover feature 21 is sometimes referred to as an “odd-jog” type feature because the crossover portion 21J spans a distance equal to one pitch, e.g., the distance between the tracks B and C in the depicted example.
To use double patterning techniques, an overall target pattern must be what is referred to as double patterning compliant. In general, this means that an overall target pattern can be decomposed into two separate patterns that each may be printed in a single layer using existing photolithography tools. An overall target pattern may have many regions or areas that cannot be printed because the features in those regions are spaced too close to one another for existing photolithography tools to be able to print such closely spaced features as individual features. To the extent an overall target pattern has an even number of such regions, such a pattern is sometimes referred to as an “even cycle” pattern, while an overall target pattern that has an odd number of such regions is sometimes referred to as an “odd cycle” pattern. Even cycle patterns can be formed using double patterning techniques, while odd cycle patterns cannot be formed using double patterning techniques.
In general, the use of patterns that have odd jog crossover or jogged features, such as the feature 21 depicted in FIG. 2B, is discouraged when trying to develop circuit layouts that are intended to be double patterning compliant for fear that the inclusion of such odd-jog crossover features will lead to odd-cycle routing layouts. However, the general restriction against using such odd-jog features for double patterning compliant circuit layouts degrade routing efficiency and may lead to the consumption of additional chip area as circuit layouts are increased in size as a result of the non-use of such odd-jog features.
FIGS. 3A-3C depict additional overall target patterns that are discussed as it relates to various issues associated with double patterning techniques. FIG. 3A depicts an illustrative circuit layout pattern 20 comprised of a plurality of rectangular line-type features 20F, e.g., trenches, and a crossover or jogged feature 22. The pattern 20 includes five illustrative routing tracks (A-E). The crossover feature 22 is a composite pattern that is comprised of line-type features 22A, 22B that are connected together by a crossover portion 22J. All of the features depicted in FIG. 2A, including the crossover portion 22J, have the same critical dimension 23. The crossover feature 22J depicted in FIG. 3A is an odd-jog type feature because the crossover portion 16J spans a distance equal to one pitch, e.g., between the tracks B and C in the depicted example. In one illustrative example, as depicted in FIG. 3A, the overall target pattern 20 may be decomposed into two sub-target patterns 20A, 20B. In this example, the crossover feature 22 is divided into two sub-features 22-1 (in pattern 20A) and 22-2 (in pattern 20B). The two sub-features 22-1, 22-2 are sized such that when these patterns are formed on a product, there will be an area or overlap 25—or a so-called “stich”—that will be printed twice, once when the mask corresponding to the pattern 20A is used and a second time when the mask corresponding to the pattern 20B is used. In this example, even though crossover or jogged feature 22 is an odd-jog feature, the pattern 20 may be formed using double patterning techniques because there is no structure near or opposite the ends 22E1 and 22E2 of the sub-features 22-1, 22-2, respectively.
FIG. 3B depicts an illustrative circuit layout pattern 30 comprised of a plurality of rectangular line-type features 30F, e.g., trenches, and a crossover or jogged feature 32. The pattern 30 includes five illustrative routing tracks (A-E). The crossover feature 32 is a composite pattern that is comprised of line-type features 32A, 32B that are connected together by a crossover portion 32J. All of the features depicted in FIG. 3B, including the crossover portion 32J, have the same critical dimension 33. The crossover feature 32 depicted in FIG. 3B is sometimes referred to as an odd-jog type feature because the crossover portion 32J spans a distance equal to three pitches, e.g., between the tracks B and E in the depicted example. In one illustrative example, as depicted in FIG. 3B, the overall target pattern 30 may be decomposed into two sub-target patterns 30A, 30B. In this example, the crossover feature 32 is divided into two sub-features 32-1 (in pattern 30A) and 32-2 (in pattern 30B). The two sub-features 32-1, 32-2 are sized such that, when these patterns are formed on a product, there will be an area or overlap 35—or a so-called “stich”—that will be printed twice, once when the mask corresponding to the pattern 30A is used and a second time when the mask corresponding to the pattern 30B is used. In this example, even though crossover or jogged feature 32 is an “odd-jog” feature, the pattern 30 may be formed using double patterning techniques because there is no structure near or opposite the ends 32E1, and 32E2 of the sub-features 32-1, 32-2, respectively.
FIG. 3C depicts an illustrative circuit layout pattern 40 comprised of a plurality of rectangular line-type features 40F, e.g., trenches, and a crossover or jogged feature 42. The pattern 40 also includes five illustrative routing tracks (A-E). The crossover feature 42 is a composite pattern that is comprised of line-type features 42A, 42B that are connected together by a crossover portion 42J. All of the features depicted in FIG. 3C, including the crossover portion 42J, have the same critical dimension 43. The crossover feature 42 depicted in FIG. 3C is sometimes referred to as an odd-jog type feature because the crossover portion 42J spans a distance equal to one pitch, e.g., between the tracks B and C in the depicted example. In this example, the overall target pattern 40 may be initially decomposed into two sub-target patterns 40A, 40B. In this example, the crossover feature 42 is divided into two sub-features 42-1 (in pattern 40A) and 42-2 (in pattern 40B). However, in this example, the overall pattern 40 cannot be formed using double patterning techniques because there is structure near or opposite the ends 42E1 and 42E2 of the sub-features 42-1, 42-2, in the areas indicated by the dashed lines 48A, 48B. That is, the spacing 45, 47 between the ends 42E1, 42E2, respectively, and the nearby structure 44, 46, respectively, violates minimum spacing design rules and, accordingly, the patterns 40A, 40B cannot be reliably formed using photolithography tools that will be used manufacturing such a pattern. Additionally, when printing certain features, the surrounding structures can and do have an impact on how accurately a feature may be formed. For example, it is known that, when trying to form a pattern like that depicted in FIG. 3C, where, for example, the end 42E1 is positioned adjacent the line 44, there will be greater variation in printing the feature 42-1 in the situation where there was an open space opposite the end 42E1. Accordingly, the overall pattern 40 depicted in FIG. 3C cannot be formed using double patterning techniques. The overall target pattern must be redesigned and/or re-routed, which results in extra time and expense and perhaps the consumption of additional area on a semiconductor chip.
The present disclosure is directed to various methods of making jogged routing layouts that are compliant with double patterning techniques which may solve or at least reduce one or more of the problems identified above.